1. Field of the Invention
This invention relates to a method for designing a semiconductor circuit and, more specifically, for carrying out a macro design at first and completing a whole circuit design after that.
2. Description of the Related Art
FIG. 9 is a flow chart to show procedures in a method for designing a semiconductor circuit based on a prior art. First, a schematic floor plan of a whole circuit is executed in a step S901. This means a schematic configuration of plural macros in the whole circuit is outlined in this step. Next, the macros are designed in a step S902. To be more precise, cells inside the plural macros and wiring are designed. After that, timing inside each macro is analyzed in a step S903. Then, presence of a timing error is checked in a step S904. If there is any timing error, a step S905 is executed. If not, a step S906 is executed.
The macro design is modified for optimizing timing in a step S905. After that, the procedure is repeated by returning to the step S903. When the timing error disappears, the step S906 is executed.
A timing model of each macro is extracted in this step S906. To be more precise, a timing model such as a response time or the like of input/output when reviewing the macro from the outside, is extracted. Next, a whole circuit is planned in steps S907 and S908. To be more precise, each macro is configured on a top layer in the step S907, and the whole circuit on the top layer is wired in the step S908. Then, a timing of the whole circuit on the top layer is analyzed in a step S909. After that, presence of a timing error is checked in a step S910. If there is, a step S911 is executed. If not, the design is completed.
The whole circuit design is modified for optimizing timing in the step S911. The possibility of modification is examined in a step S912. If possible, timing of the whole circuit after modification is analyzed by returning to the step S909. If impossible, the design inside the macro is modified by returning to the step S905. This means if a timing error is not completely modified by just modifying the whole circuit design, returning to the macro design procedure is inevitable. These procedures must be repeated until timing errors of both macros and the whole circuit completely disappear.
This method for designing the semiconductor circuit comprises a procedure for returning to the step S903 due to an error found in the step S904, and a procedure for returning to the steps S909 and S905 due to an error found in the step S910. Especially, the one for returning to the step S905 due to the error found in the step S910 greatly influences entire design time.
In a development of the latest LSI (Large Scale Integration), timing margin decreases according to the rise of operating frequency. Therefore, an ideal optimization for satisfying all conditions is getting more and more difficult. As a result, the number of procedures for returning to a previous one has increased and time for designing has multiplied.
For example, when a timing error happens due to signal delay of a long external wiring which surrounds a large macro, returning to the step S905 is required due to the error found in the step S910. A typical example will hereunder be described, in which a timing error after timing analysis of a whole circuit on a top layer is found.
FIG. 10A is a view to show a wiring of the whole circuit on the top layer wired in the above-described step S908. An external wiring 1003 is a wiring for connecting nodes 1001 with 1002, and it surrounds a macro 1000. If a timing error is found in the step S910, the wiring length of the external wiring 1003 must be shortened. However, if it cannot be shorter than the present one, it is concluded at the step S912 that modification is impossible. Therefore, returning to step S905 is required.
As can be seen in FIG. 10B, by modifying the macro design in the step S905, external terminals 1011 and 1012 are then provided in the macro 1000, and an internal wiring for connecting them is also provided. The external wirings 1013 are wired in the step S908. The external wirings 1013 connect the nodes 1001 and 1002 via the external terminals 1011 and 1012. Then, a timing error disappears due to shorter length of the wirings between the nodes 1001 and 1002 and shorter delay time. However, even if this timing error is eliminated at the step S910, another timing error may happen in another portion of the whole circuit due to the above-described design modification.
As can be seen in FIG. 10C, the macro 1000 must be often rotated by 90° in the step S911. In this case, longer external wirings 1021 which connect the nodes 1001 and 1002 are required, and delay time also becomes longer. A procedure for returning to the step S905 must be performed due to an error found in the step S910.
Modification of a portion which does not satisfy conditions due to a timing error influences another portion and requires adjustment of timing again. Repetition of such procedures aggravates convergence of the design. In the case that the same type of plural macros are configured on a top layer, when configuration and wiring inside the macro is modified for eliminating a timing error of a whole circuit on the top layer, this macro is required to be handled as another.